Mercurial > libervia-backend

diff src/bridge/bridge_constructor/dbus_core_template.py @ 1026:71fdc327b318

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core: getReady and asyncConnect now wait full initialisation, not only memory
author Goffi <goffi@goffi.org>
date Thu, 15 May 2014 20:01:56 +0200
parents 301b342c697a
children 95758ef3faa8
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