Mercurial > libervia-backend
view .hgignore @ 1026:71fdc327b318
core: getReady and asyncConnect now wait full initialisation, not only memory
author | Goffi <goffi@goffi.org> |
---|---|
date | Thu, 15 May 2014 20:01:56 +0200 |
parents | af900f49df89 |
children | f2cb99b196b1 |
line wrap: on
line source
syntax: glob *.pyc *.pyv *.swp *.swo tags twistd.log twistd.pid bridge_constructor/generated _trial_temp/ sat.egg-info *.un~ dist MANIFEST build ctags_links/